Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell
US5841695A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 1997 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | May 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit comprises a memory cell array and a data sense module. Each cell of the array includes a first, second and third transistors, and a capacitance. The first transistor has a first gate coupled to a first word line, a floating gate which stores a first charge, a first source coupled to a first data line, and a first drain. The second transistor has a second gate coupled to the first drain, a second source coupled to a second word line, and a second drain. The third transistor has a third gate coupled to a third word line, a third source coupled to the second drain, and a third drain coupled to a second data line. The capacitance is coupled between ground and the third source. The capacitance stores a second charge when the second word line is asserted and the third word line is de-asserted. The second gate stores a third charge when the first word line is de-asserted. The data sense module is coupled to the first and second data lines, and configured to sense the second charge if the third word line is asserted while the second word line is asserted. The data sens…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.