First-in, first-out (FIFO) buffer
US5841722A · kind A · utility
71Cited by
3References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 13, 1997 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Feb 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A variable sized FIFO buffer whose size changes in accordance with how much data is present to be passed between the two systems is provided. One embodiment of the FIFO buffer includes at least one lower FIFO, at least one upper FIFO, a RAM and a controller. The upper FIFO buffer receives data from a first system and the lower FIFO buffer writes data to a second system. The RAM is utilized when data can no longer flow between the upper and lower FIFO buffers, due to the lower FIFO buffer being temporarily full.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.