Information handling system having a register remap structure using a content addressable table
US5841999A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1996 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Apr 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes an instruction unit, one or more execution units, a memory management unit, connected to the instruction unit, to a memory system, a cache management unit, one or more levels of cache memory associated with the one or more execution units, one or more I/O controllers connected to a bus which connects to the execution units and to the memory systems and to cache, and a completion unit for tracking sequence of instruction dispatch and instruction completion. The completion unit includes a Content Addressable Register Buffer Assignment Table, a Register Status Table, an Instruction Queue, and a Completion Table to control order of execution and completion of instructions in a sequence dependent on availability of operands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.