Erdem Hokenek
25Patents
12h-index
19Co-inventors
78Inventor score
Filing activity: Oct 7, 1988 → Oct 27, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6971103B2 | Inter-thread communications using shared interrupt register | Physics | 50 | Expired |
| US6842848B2 | Method and apparatus for token triggered multithreading | Physics | 44 | Expired |
| US6665790B1 | Vector register file with arbitrary vector addressing | Physics | 41 | Expired |
| US4926369A | Leading 0/1 anticipator (LZA) | Physics | 41 | Expired |
| US6904511B2 | Method and apparatus for register file port reduction in a multithreaded processor | Physics | 28 | Expired |
| US6990557B2 | Method and apparatus for multithreaded cache with cache eviction based on thread identifier | Physics | 21 | Expired |
| US7467288B2 | Vector register file with arbitrary vector addressing | Physics | 18 | Expired |
| US6925643B2 | Method and apparatus for thread-based memory access in a multithreaded processor | Emerging Cross-Sectional Technologies | 15 | Expired |
| US6968445B2 | Multithreaded processor with efficient processing for convergence device applications | Physics | 14 | Expired |
| US7475222B2 | Multi-threaded processor having compound instruction and operation formats | Physics | 13 | Expired |
| US7797363B2 | Processor having parallel vector multiply and reduce operations with sequential semantics | Physics | 12 | Active |
| US8074051B2 | Multithreaded processor with multiple concurrent pipelines per thread | Physics | 12 | Expired |
| US6269039A | System and method for refreshing memory devices | Physics | 11 | Expired |
| US7428567B2 | Arithmetic unit for addition or subtraction with preliminary saturation detection | Physics | 10 | Active |
| US6912623B2 | Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy | Emerging Cross-Sectional Technologies | 10 | Expired |
| US7356673B2 | System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form | Physics | 8 | Expired |
| US5841999A | Information handling system having a register remap structure using a content addressable table | Physics | 8 | Expired |
| US7308559B2 | Digital signal processor with cascaded SIMD organization | Physics | 5 | Expired |
| US7209529B2 | Doppler compensated receiver | Emerging Cross-Sectional Technologies | 4 | Expired |
| US6990509B2 | Ultra low power adder with sum synchronization | Physics | 2 | Expired |
| US8892849B2 | Multithreaded processor with multiple concurrent pipelines per thread | Physics | 2 | Active |
| US8762688B2 | Multithreaded processor with multiple concurrent pipelines per thread | Physics | 1 | Active |
| US8959315B2 | Multithreaded processor with multiple concurrent pipelines per thread | Physics | 0 | Active |
| US8918627B2 | Multithreaded processor with multiple concurrent pipelines per thread | Physics | 0 | Active |
| US7055102B2 | Turbo decoder using parallel processing | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.