Power MOSFETs and cell topology

US5844277A · kind A · utility

Assignee

• Magepower Semiconductor Corp. · US

Inventors

• Fwu-Iuan Hshieh · Saratoga, US
• True-Lon Lin · Cupertino, US

Key dates

• Filing date: Feb 20, 1996
• Grant date: Dec 1, 1998
• Expiry date: Feb 20, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/111

Abstract

A MOSFET device formed in a semiconductor chip with a top surface and a bottom surface. The MOSFET device includes a drain region doped with impurities of a first conductivity type, formed near the bottom surface. The MOSFET device further includes a plurality of vertical cells wherein each of the vertical cell includes a vertical pn-junction zone region includes a lower-outer body region, doped with impurities of a second conductivity type, formed on top of the drain region. The pn-junction region further includes a source region, doped with impurities of the first conductivity type, formed on top of the lower-outer body region, the lower-outer body region surrounding the source region and extending to the top surface thus defining a cell area for the cell. The vertical cell further includes a source contact formed on the top surface contacting the source region. The MOSFET further includes a plurality of gates. Each gate is formed on the top surface as a poly layer extending from an area near a boundary of the source region and the lower-outer body region of one of the cells to a neighboring cell, the gate includes a thin insulative bottom layer for insulating from the vertical c…