State saving and restoration in reprogrammable FPGAs
US5844422A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1996 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Nov 13, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Structures for saving states of memory cells in an FPGA while the FPGA is being configured are shown. Structures for saving flip flop states, lookup table configurations, and block RAM states are specifically described. Structures are described having (1) a SAVE STATE bit for saving the state of each flip flop, each lookup table RAM, and each block RAM. With these structures, each storage unit can be selectively restored. (2) a SAVE STATE bit for each row(column) of logic blocks in the FPGA. In such structures it is possible with a single SAVE STATE signal to selectively save or restore every memory element in the row, possibly including flip flops, lookup tables, and blocks of RAM. Several structures and methods for providing the SAVE STATE signal are also described. These include: (1) bits in the bitstream of a first configuration which indicate which memory units of the first configuration are to be retained during a second configuration; (2) bits at the beginning of the bitstream of a second configuration which indicate which memory units of the first configuration are to be retained during a second configuration; and (3) circuit loadable during operation of a first configurati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.