Configurable parallel and bit serial load apparatus
US5844829A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1997 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Dec 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17748
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.