Cell array structure for a ferroelectric semiconductor memory and a method for sensing data from the same
US5844832A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 1997 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Aug 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric semiconductor random access memory (RAM) is disclosed, which comprises a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells having an access transistor and a ferroelectric capacitor, a plurality of bit lines of open bit line structure connected with corresponding sense amplifiers, and a plurality of reference cells arranged symmetrically against the sense amplifiers for providing reference voltage to the reference input terminals of the sense amplifiers toe sense the logical states of the data stored in the memory cells. In this device, the reference voltage is provided from one of the reference cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.