Single-electron memory cell configuration

US5844834A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Lothar Risch · Neubiberg, DE
• Wolfgang Rosner · Hersbruck, DE

Key dates

• Filing date: Jun 2, 1997
• Grant date: Dec 1, 1998
• Expiry date: Jun 2, 2017

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/937
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Each memory cell of an array has a single-electron transistor and a single-electron memory element. The single-electron transistor is driven by a charge stored in the memory element. When a read voltage is applied, a current flows through the single-electron transistor which is dependent on the stored charge, but the stored charge in not changed. When a write voltage is applied, the magnitude of which is greater than the read voltage, then the stored charge is changed. The memory cells of the array are each connected between first lines and transverse second lines of a memory cell configuration.