Adaptive arbitration mechanism for a shared multi-master bus
US5845096A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1996 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Aug 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for determining which of plurality of peripheral components will have access to a peripheral component interconnect (PCI) bus when none of the plurality of peripheral components is currently requesting access to the PCI bus. In one embodiment a history buffer records all requests by a plurality of peripheral components for access to the PCI bus. The present invention then determines which of the plurality of peripheral components requests access to the PCI bus most often. Next, the present invention grants the peripheral component which requests access to the PCI bus most often access to the PCI bus when no other peripheral component is requesting access to the PCI bus. In so doing, the present invention "parks" the PCI bus on the peripheral component which has, in the past, requested access to the PCI bus most often.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.