Method for simulating cache operation
US5845106A · kind A · utility
15Cited by
6References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 26, 1996 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Jan 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple functional units of a computer system that typically access a secondary cache and the main memory system independently and simultaneously are simulated using RTL models which create such accesses using a random process. In one embodiment, an RTL model of each functional unit generates accesses to the cache memory according to a programmable frequency. The RTL models of these functional units also generate addresses which fall within programmable address limits and tag limits. In one embodiment, the functional units include data and instruction table lookaside buffers which traverse a two-level address translation scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.