Mailbox traffic controller
US5845130A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1996 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Sep 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for preventing contention in a shared memory environment. In one embodiment, a first processor reads a traffic controller which is coupled to a shared memory and to a second processor. The first processor writes its identifier into the traffic controller provided that the traffic controller does not already have an identifier corresponding to the second processor stored therein. If the traffic controller does have an identifier corresponding to the second processor stored therein, the first processor periodically reads the traffic controller until the traffic controller does not have an identifier corresponding to the second processor stored therein. Once the traffic controller has the identifier corresponding to the first processor stored therein, the traffic controller allows the first processor to control access to the shared memory. Once the first processor controls access to the shared memory, the second processor knows that it must wait before attempting to control access to the shared memory. In so doing, the present invention eliminates contention between the first and second processors for control of the shared memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.