Floating bitline test mode with digitally controllable bitline equalizers
US5848008A · kind A · utility
4Cited by
7References
11Claims
0Family size
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Key dates
| Filing date | Sep 25, 1997 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | Sep 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.