Address enable circuit in synchronous SRAM
US5848022A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 1997 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | May 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel address enable circuit for use in a synchronous memory that includes a memory core. The address enable circuit includes an address latching circuit that outputs a synchronized address and latches a pre-decoded address when an input clock signal transitions from a first logical level to a second logical level so that the synchronized address identifies the pre-decoded address. The address enable circuit also includes a reset circuit that generates a reset signal that (1) does not indicate a reset when the latched chip enable signal indicates that the memory has been selected while the clock signal is at the second logical level, (2) indicates a reset when the latched chip enable signal indicates that the memory has not been selected while the clock signal is at the second logical level, and (3) does not indicate a reset while the clock signal is at the first logical level. The address latching circuit is reset when the reset signal indicates a reset so that the synchronized address identifies a disabled address that indicates that memory access to the memory core is disabled and is not reset when the reset signal does not indicate a reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.