Method and apparatus for address disambiguation using address component identifiers
US5848256A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scheduling unit is described for scheduling an execution order of a first instruction of a first type and a second instruction of a second type in an instruction stream where the second instruction precedes the first instruction. The scheduling unit comprises a table that records address component identifiers corresponding to the second instruction. An address comparator is coupled to the table. The address comparator compares address component identifiers that corresponds to the first instruction with address component identifiers on the table. The scheduling unit schedules the first instruction to be executed ahead of the second instruction when the address component identifiers differ from the address component identifiers on the table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.