Michael J. Morrison
32Patents
13h-index
25Co-inventors
81Inventor score
Filing activity: Sep 30, 1996 → Feb 18, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6151669A | Methods and apparatus for efficient control of floating-point status register | Physics | 101 | Expired |
| US5880985A | Efficient combined array for 2n bit n bit multiplications | Physics | 44 | Expired |
| US6301705A | System and method for deferring exceptions generated during speculative execution | Physics | 41 | Expired |
| US5961630A | Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency | Physics | 40 | Expired |
| US6223278A | Method and apparatus for floating point (FP) status word handling in an out-of-order (000) Processor Pipeline | Physics | 28 | Expired |
| US5996064A | Method and apparatus for guaranteeing minimum variable schedule distance by using post-ready latency | Physics | 25 | Expired |
| US6170052A | Method and apparatus for implementing predicated sequences in a processor with renaming | Physics | 20 | Expired |
| US5918031A | Computer utilizing special micro-operations for encoding of multiple variant code flows | Physics | 18 | Expired |
| US6249798A | Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unit | Electricity | 18 | Expired |
| US6578059B1 | Methods and apparatus for controlling exponent range in floating-point calculations | Physics | 16 | Expired |
| US6279102A | Method and apparatus employing a single table for renaming more than one class of register | Physics | 15 | Expired |
| US5848256A | Method and apparatus for address disambiguation using address component identifiers | Physics | 14 | Expired |
| US6370639B1 | Processor architecture having two or more floating-point status fields | Physics | 14 | Expired |
| US6094713A | Method and apparatus for detecting address range overlaps | Physics | 12 | Expired |
| US6412067B1 | Backing out of a processor architectural state | Physics | 11 | Expired |
| US6212539A | Methods and apparatus for handling and storing bi-endian words in a floating-point processor | Physics | 8 | Expired |
| US8635417B2 | Memory system including variable write command scheduling | Physics | 7 | Active |
| US5954814A | System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipeline | Physics | 6 | Expired |
| US10114558B2 | Integrated main memory and coprocessor with low latency | Physics | 5 | Active |
| US8527676B2 | Reducing latency in serializer-deserializer links | Physics | 5 | Active |
| US8832336B2 | Reducing latency in serializer-deserializer links | Physics | 4 | Active |
| US5961615A | Method and apparatus for queuing data | Physics | 4 | Expired |
| US9354823B2 | Memory system including variable write burst and broadcast command scheduling | Physics | 3 | Active |
| US11221764B2 | Partitioned memory with shared memory resources and configurable functions | Physics | 2 | Active |
| US6216221A | Method and apparatus for expanding instructions | Physics | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.