Method of forming a low stress polycide conductors on a semiconductor chip
US5849629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1995 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Oct 31, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. Various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.