Patent · US Expired

System and method for validating interrupts before presentation to a CPU

US5850555A · kind A · utility

9Cited by

34References

17Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Qadeer A. Qureshi · Dripping Springs, US
Joseph A. Bailey · Austin, US
Dan S. Mudgett · Austin, US

Key dates

Filing date	Dec 19, 1995
Grant date	Dec 15, 1998
Priority date	—
Expiry date	Dec 19, 2015

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/24
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity checker monitors the state of each interrupt request as it is processed through the interrupt controller. The interrupt request is canceled if the interrupt request becomes invalid. Alternatively, the programmable interrupt controller issues a spurious interrupt vector if the interrupt request becomes invalid after a CPU has responded.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.