System and method for referencing interrupt request information in a programmable interrupt controller
US5850558A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1995 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Dec 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An unique interrupt identification code is assigned to each interrupt request and used to reference information in the storage device associated with each interrupt request. The interrupt request interface uses the unique interrupt identification code to access the information for each interrupt request and determine if the interrupt request should proceed to one of the processor interfaces. The processor interface uses the unique interrupt identification code to access the information in order to determine if and when the interrupt request should issue to one of the CPUs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.