Process for manufacturing integrated capacitors in MOS technology
US5851871A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 3, 1996 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Jul 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
A process for manufacturing integrated capacitors in CMOS technology, comprising the steps of: producing, in a substrate of semiconductor material having a first type of conductivity, at least one well with the opposite type of conductivity, defining the active areas, producing insulation regions, depositing a first conducting layer of polycrystalline silicon adapted to form the gate regions and the lower plates of the capacitors, depositing a layer of silicon oxide at low temperature, to form the dielectric of the capacitors, depositing a second layer of polycrystalline silicon to form the second plate of the capacitors, shaping the polycrystalline silicon and silicon oxide layers, implanting and diffusing the source and drain regions of the CMOS transistors, providing the insulation layer, the metallic connecting layer, and final covering with a layer of protective insulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.