Gapfill and planarization process for shallow trench isolation

US5851899A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventor

• Peter Weigand · Unterhaching, DE

Key dates

• Filing date: Aug 8, 1996
• Grant date: Dec 22, 1998
• Expiry date: Aug 8, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76229
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Described is a method for filling shallow trench isolation (STI) trenches in a semiconductor substrate of an integrated circuit with an insulating material and planarizing the resulting structure to the level of adjacent portions of the integrated circuit. The method comprises forming trenches in the non-active regions of a semiconductor substrate, depositing a layer of oxide in the trenches and over the surface of the semiconductor substrate, and removing the oxide from the active areas of the integrated circuit structure, leaving oxide-filled shallow trench isolation structures having a substantially planar topography with respect to the rest of the integrated circuit structure.