Flash memory cell structure having a high gate-coupling coefficient and a select gate
US5852313A · kind A · utility
4Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1997 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Nov 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.