Pattern generator circuit for semiconductor test system
US5852619A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1997 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Dec 8, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31813
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A pattern generator that makes it possible to use various option pattern generators (PGs) without changing hardware is realized. To accomplish this, an option circuit includes an option PG initial clock control section that generates an initial clock signal in synchronism with a clock signal to initialize the option PGs; a plurality of option PGs selectively receive one of a plurality of clock output signals of a clock output control section and generate pattern and clock signals; and in a multiplexer which selects one of output signals from the plurality of PGs through an instruction from a select register 24, and a FIFO section which receives a signal from the multiplexer as write data and a write clock, and an output signal of a read clock control section as a read clock, and outputs a signal to a logic circuit as the option PG output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.