Dummy fill patterns to improve interconnect planarity
US5854125A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 1997 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Feb 24, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of improving the planarity of spin-on glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces on a trace layer of a semiconductor wafer that exceed a predetermined threshold distance are provided with dummy surfaces arranged in a micro-pattern in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined threshold distance is greater than approximately 2 micrometers, as for example in the range of approximately 4.65 to 5 micrometers. In some applications, both the active conductive traces and the dummy surfaces are formed from a metallic material that is deposited in one single step with a dielectric layer being deposited over both the active conductive traces and the dummy surfaces prior to application of the spin-on glass layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.