Semiconductor IC with a plurality of processing circuits which receive parallel data via a parallel data transfer circuit
US5854636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1997 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Sep 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit having a two-dimensional array (MAR) and a parallel data transfer circuit (TRC) for transferring from the array data read out in parallel through data lines, in parallel to a processing circuit group (PE) by selecting the word lines of the two-dimensional memory array. The processing circuit group executing processing operations in parallel by using the data transferred from the parallel data transfer circuit. Each of the processing circuits having access to a plurality of series word lines and the data lines of the two-dimensional array through the parallel data transfer circuits. The arrangement of the parallel data transfer circuits allowing for an overlap range wherein data from each of the data lines of the memory array is available to more than one of the parallel data transfer circuits. Since the data lines of the two-dimensional memory array have the overlapped range, convolution processing operations or the like can be executed in parallel for the two-dimensional data stored in the two-dimensional memory array in a high parallelism and at a high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.