Unified memory architecture with parallel access by host and video controller
US5854638A · kind A · utility
38Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 2, 1996 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Feb 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a unified memory computer system architecture, the unified memory is divided into at least two banks of memory. All but one of the memory banks is reserved for access exclusively by the host memory controller, and only one bank of memory is shared between the host memory controller and the video controller. Host accesses to the non-shared bank of the unified memory can take place concurrently with video controller accesses to the shared bank of memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.