Integrated circuit with non-binary decoding and data access
US5854763A · kind A · utility
38Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1997 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Jan 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention describes an addressing and data access method and apparatus which can make use of maximum sized, binary configured blocks of memory or macro cells. The binary sized blocks of memory may be used to implement a non-binary sized overall memory circuit. The apparatus as described makes efficient use of silicon area by combining an optimized number of memory blocks or macro cells having at least two data port per macro cell to implement a non-binary sized memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.