Sectorized electrically erasable and programmable non-volatile memory device with redundancy
US5854764A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1997 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Mar 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sectorized electrically erasable and programmable non-volatile memory device comprises: a plurality of individually-addressable memory sectors, each memory sector comprising an array of memory cells arranged in rows and columns; redundancy columns of redundancy memory cells for replacing defective columns of memory cells; and a redundancy control circuit for storing addresses of the defective columns and activating respective redundancy columns when said defective columns are addressed. Each memory sector comprises at least one respective redundancy column. The redundancy control circuit comprises at least one memory means comprising individually addressable memory locations each one associated with a respective memory sector for storing, individually for each memory sector, addresses of a defective column belonging to the memory sector, and an address recognition means associated with said memory means for recognizing if a current address supplied to the memory device coincides with a defective column address stored in an addressed one of said memory locations associated with a currently addressed memory sector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.