Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication
US5855693A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1995 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Dec 13, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer of semiconductor material for fabricating integrated devices, including a stack of superimposed layers including first and second monocrystalline silicon layers separated by an intermediate insulating layer made of a material selected from the group comprising silicon carbide, silicon nitride and ceramic materials. An oxide bond layer is provided between the intermediate layer and the second silicon layer. The wafer is fabricated by forming the intermediate insulating layer on the first silicon layer in a heated vacuum chamber; depositing the oxide layer; and superimposing the second silicon layer. When the stack of silicon, insulating material, oxide and silicon layers is heat treated, the oxide reacts so as to bond the insulating layer to the second silicon layer. As a ceramic material beryllium oxide, aluminium nitride, boron nitride and alumina may be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.