Method of fabricating a low voltage zener-triggered SCR for ESD protection in integrated circuits
US5856214A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1996 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Mar 4, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/983
Abstract
The method in accordance with the present invention is compatible with conventional CMOS fabrication processes to form a zener diode and a lateral silicon controlled rectifier constituting an on-chip ESD protection circuit in a semiconductor substrate. The zener diode is composed of a p-type doped region and an n-type doped region, wherein one of the doped regions, formed by deep diffusing impurities from a doped polysilicon layer, is arranged between two adjacent well regions. During an ESD event, the zener diode incurs breakdown to lower the trigger voltage of the lateral SCR device to within a range of about 5-7 Volts to thereby discharge the ESD current prior to damage of an internal circuit being protected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.