Method for manufacturing self-aligned split-gate flash memory cells
US5856223A · kind A · utility
17Cited by
4References
18Claims
0Family size
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Inventor
Key dates
| Filing date | May 21, 1997 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | May 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
A method for manufacturing self-aligned split-gate flash memory cells wherein the split-gate structure is formed by a self-aligned approach, so that the length of a channel can be precisely controlled. Furthermore, sources and drains are formed separately by executing different implantations, so that the dopant parameters of the sources and drains can be changed, based on desired and possibly different characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.