Logic speed-up by selecting true/false combinations with the slowest logic signal
US5856746A · kind A · utility
3Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1996 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Jun 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A "slow" signal is not sent across chip to be combined with combinatorial logic, but rather, the logic with which it would be combined is partitioned such that there are two outputs, one if the "slow" signal would be true and a second if the "slow" signal would be false. Both of these outputs are then provided to a multiplexer. The original "slow" signal selects the correct signal, thus saving the interconnect time delay. The concepts also apply to combinations of multiple "slow" signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.