Small-sized multi-valued semiconductor memory device with coupled capacitors between divided bit lines
US5856938A · kind A · utility
13Cited by
5References
36Claims
0Family size
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Key dates
| Filing date | Feb 24, 1997 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Feb 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a 2.sup.m (m=1, 2, . . . )-valued semiconductor memory device, including a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells each connected to one of the word lines and one bit line of the bit line pairs, each of the bit line pairs are divided into m divided bit line pairs, and a ratio of capacitances of the m divided bit line pairs is 1:2: . . . :2.sup.m-1. Also, each sense amplifier is connected to one of the bit line pairs. Further, each of coupled capacitor pairs is cross-coupled between two adjacent divided bit line pairs of the divided bit line pairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.