Scalable flash EEPROM memory cell and array
US5856943A · kind A · utility
64Cited by
16References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.