Integrated Memory Technologies, Inc.
20Patents
0Active
20Granted
30Portfolio score
Filing activity: Jan 31, 1997 → Jan 23, 2006
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5856943A | Scalable flash EEPROM memory cell and array | Electricity | 64 | Expired |
| US6057575A | Scalable flash EEPROM memory cell, method of manufacturing and operation thereof | Electricity | 61 | Expired |
| US5912843A | Scalable flash EEPROM memory cell, method of manufacturing and operation thereof | Electricity | 56 | Expired |
| US6232185A | Method of making a floating gate memory cell | Electricity | 48 | Expired |
| US6134144A | Flash memory array | Electricity | 47 | Expired |
| US6377507B1 | Non-volatile memory device having high speed page mode operation | Physics | 36 | Expired |
| US6556508B2 | Integrated circuit memory device having interleaved read and program capabilities and methods of operating same | Physics | 28 | Expired |
| US6496415B2 | Non-volatile memory device having high speed page mode operation | Physics | 24 | Expired |
| US6764905B2 | Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate | Electricity | 21 | Expired |
| US6469955B1 | Integrated circuit memory device having interleaved read and program capabilities and methods of operating same | Physics | 18 | Expired |
| US6134149A | Method and apparatus for reducing high current during chip erase in flash memories | Physics | 17 | Expired |
| US6507514B1 | Integrated circuit memory chip for use in single or multi-chip packaging | Physics | 15 | Expired |
| US6621115B2 | Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate | Electricity | 14 | Expired |
| US6614715B2 | Integrated circuit memory device having interleaved read and program capabilities and methods of operating same | Physics | 12 | Expired |
| US5886887A | Voltage multiplier with low threshold voltage sensitivity | Electricity | 7 | Expired |
| US7009244B2 | Scalable flash EEPROM memory cell with notched floating gate and graded source region | Physics | 7 | Expired |
| US6967870B2 | Combination NAND-NOR memory device | Physics | 6 | Expired |
| US7407857B2 | Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region | Physics | 5 | Expired |
| US6259625A | Method and apparatus for reducing high current chip erase in flash memories | Physics | 1 | Expired |
| US7199424B2 | Scalable flash EEPROM memory cell with notched floating gate and graded source region | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.