High-speed disturb testing method and word line decoder in semiconductor memory device
US5856982A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1996 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Dec 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed disturb testing method for a semiconductor memory device is disclosed, includes the steps of: (a) writing first piece of data in all of the memory cells in the memory cell array; (b) reading and confirming the first piece data written in each memory cell of the memory cell array; (c) writing second piece data in all of the memory cells connected to the plurality of disturb word lines; (d) reading and confirming the second piece data from all of the memory cells (e) fixing the mode of the disturb word line to the test mode; (f) repeatedly writing the second piece data in all of the memory cells connected to the plurality of disturb word lines; (g) changing the test mode to the normal mode; (h) refreshing all of the memory cells; (i) reading and confirming the first piece data from a word line located close to the selected plurality of disturb word lines; (j) writing the first piece data in all of memory cells connected to the plurality of disturb word lines; (k) repeating the steps (3) to (10), to thereby apply disturb to all of the word lines one by one; and (l) reading and confirming the first piece data from the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.