Process for fabricating a high performance logic and embedded dram devices on a single semiconductor chip

US5858831A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventor

• Janmye Sung · Taipei, TW

Key dates

• Filing date: Feb 27, 1998
• Grant date: Jan 12, 1999
• Expiry date: Feb 27, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A process for creating a region of high performance logic devices, and a region of low cost memory devices, on a single semiconductor chip, has been developed. The process features CMOS logic devices, comprised of polycide gate structures, residing on a thin silicon dioxide gate insulator layer. An N type polysilicon layer, used as part of a polycide structure, is used with the N channel CMOS devices, while a P type polysilicon layer, is used with the P channel CMOS devices. DRAM memory devices are comprised of polycide gate structures, featuring only an N type polysilicon layer, on a silicon dioxide gate insulator layer, that is thicker than the gate silicon oxide layer used with the high performance logic devices. A minimum of additional photolithographic masking procedures is used to improve the performance of the logic region, one mask to allow specific polycide gate structures to be created with either P type or N type polysilicon, and another additional mask used to allow different gate insulator layers to be formed in each specific region. A large angle, ion implantation procedure, is used to form lightly doped source and drain regions, under the silicon nitride spacers on t…