Simultaneous deposit and etch method for forming a void-free and gap-filling insulator layer upon a patterned substrate layer
US5858876A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 1996 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Apr 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a void-free and gap-filling doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit. Formed upon a semiconductor substrate is a patterned substrate layer. Formed upon the patterned substrate layer is a doped silicon oxide insulator layer. The doped silicon oxide insulator layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method. The Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employ a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.