Semiconductor memory having storage capacitor connected to diffusion region through barrier layer
US5859451A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 19, 1991 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Jun 19, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
Abstract
A memory cell comprising a MOSFET formed on a principle surface of a semiconductor substrate and an information storage capacitor having a storage electrode formed in or on the substrate so as to contact with a drain region of the MOSFET, and a capacitor electrode formed adjacent to the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. The storage electrode is connected to the drain region of the MOSFET through a thin barrier layer which is formed between the drain region and the storage electrode region so as to prevent impurities in the storage electrode from being diffused into the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.