Multi-level memory circuits and corresponding reading and writing methods
US5859795A · kind A · utility
37Cited by
2References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 30, 1997 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Jan 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory circuit of the multi-level type, i.e. a memory circuit having a plurality of memory elements, each adapted to store more than one binary information unit, wherein the memory elements are utilized for storing a number of binary information units tied to an acceptable error rate for a particular application: typically, one bit where a low error rate is sought, and two bits where a higher error rate can be accepted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.