Biasing circuit for UPROM cells with low voltage supply
US5859797A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1997 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Apr 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.