System for receiving burst width greater than cache width by storing first portion of burst to cache and storing second portion of burst to storage circuit
US5860027A · kind A · utility
5Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1997 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Apr 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.