Conflict cache having cache miscounters for a computer memory system
US5860095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1996 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Jan 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer memory cache system that includes hardware (called a conflict cache) for short term tolerance and reduction of cache misses and including counters to enable software to detect and remove longer term cache misses through dynamic page remapping. In an example embodiment, when a conflict miss occurs for a low associativity cache, the address of the displaced item is saved in a content addressable memory and the corresponding data is saved in a data RAM. The operating system logically partitions the low associativity cache into bins, where the address range for a bin is a page or multiple pages. Every logical bin in the low associativity cache has a corresponding counter in the conflict cache. Each bin counter counts the number of conflict misses for the corresponding bin. When a bin counter exceeds a predetermined value, the operating system remaps a corresponding page. For a multiple level cache hierarchy, the top level cache is made a subset of the union of a lower level direct mapped cache and the conflict cache. This inclusion property prolongs the life of cache lines in the top level cache in the presence of conflict misses, improving the top level cache performance. I…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.