Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an asynchronous partial reset and an asynchronous master reset
US5860125A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1995 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Nov 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is provided which comprises a core section, a plurality of input/output sections, and a pair of reset inputs. The first reset input is a master reset which initializes the entire integrated circuit. The second reset input is a partial reset. The partial reset initializes a portion of the integrated circuit while other portions remain in operation. The core section can include a plurality of subsystems such as a real time clock facility, a configuration RAM, and a DRAM memory controller. The real time clock facility and configuration RAM are not affected by the partial reset. Accordingly, the real time clock is maintained during partial reset, thereby maintaining accurate time/date and configuration data during partial reset. The DRAM controller is optionally reset based on a configuration bit stored in a configuration register in one of the plurality of subsystems. When not reset, the DRAM controller provides refresh to an array of DRAM memory cells, thereby maintaining the data stored within the DRAM memory cells. The integrated circuit can be configured into a personal information device, wherein a power conservation method can then be applied by resetting p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.