Instruction pre-fetching of a cache line within a processor
US5860150A · kind A · utility
13Cited by
12References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 6, 1995 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Oct 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for fetching data from a main memory into a primary cache memory of a processor. Instruction fetch requests are generated by the processor and assigned a priority level according to the predicted accuracy of the fetch request. The priority levels of different fetch requests are compared and the highest priority level fetch request is serviced first. An instruction cache line address N+1 is pre-fetched if there is a cache miss in the primary cache memory on address N+1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.