Fabrication method of gate electrode in semiconductor device
US5861327A · kind A · utility
8Cited by
1References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1997 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Jul 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28587
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method of a semiconductor device is disclosed. A T-shaped gate used for decreasing the gate resistance is adopted in fabricating an ultrahigh frequency and low-noise device. According to the present invention, a gate pattern is formed by a dual exposure technique, a thin metal film is formed, a pattern for plating is formed, and a gate is formed by electroplating, whereby decreasing a gate length and gate resistance. Therefore, the cost of production is decreased, the yield is improved, and the noise figure is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.