Stacked chip assembly
US5861666A · kind A · utility
309Cited by
29References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An assembly of semiconductor chips has the chips vertically stacked above one another. Interposers extending between adjacent chips have compliant layers to accommodate thermal expansion of the chips. Desirably, the interposers have metallic plates to conduct heat from the interior of the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.