Semiconductor package
US5861668A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 1997 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Jan 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package of the present invention includes a paddle layer having a metal wiring pattern formed therein, semiconductor chips bonded on at least one surface of the paddle layer. A plurality of wires electrically connecting a plurality of chip pads formed on the semiconductor chips with the paddle layer. Each lead includes a first lead bonded to a surface of the paddle layer and a second lead which is at least partially exposed. A conductive adhesive bonds the paddle layer to the first leads and a molding resin comprises the body of the package. The semiconductor package of the above construction has various advantages compared to conventional packages. The occupying area rate can be minimized, and an undesired curving of the lead can be prevented. Further, since the semiconductor chip can be bonded on both surfaces of the paddle layer, an integrated semiconductor package can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.