Method and memory device for dynamic cell plate sensing with ac equilibrate
US5862089A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1997 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Aug 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device that uses a dynamic cell plate sensing scheme. The memory device includes an array of word lines and complementary bit line/plate line pairs. A number of memory cells are located at the intersection of selected word lines and bit line/plate line pairs. A sense amplifier is coupled to the complementary bit line/plate line pairs. The memory device also includes an equilibrate circuit that ac equilibrates a complementary bit line/plate line pair at an equilibration voltage between high and low logic levels prior to reading data. The equilibration voltage and the high and low logic levels for the memory cell are chosen such that a fluctuation in the voltage on one of the plate lines does not corrupt data stored in unaccessed memory cells coupled to the same plate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.