Control circuit for deterministic stopping of an integrated circuit internal clock
US5864564A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1995 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Nov 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A control circuit to stop an integrated circuit internal clock includes a signal distribution trace connected to a clock stop pipeline. The signal distribution trace creates a large phase delay signal for a first integrated circuit internal clock cycle which activates the clock stop pipeline, and a small phase delay signal for a final integrated circuit internal clock cycle that deactivates the clock stop pipeline. The clock stop pipeline includes a first circuit component to generate an intermediate stop instruction in response to a clock stop command and the large phase delay signal of the first integrated circuit internal clock cycle. The intermediate stop instruction proceeds through the clock stop pipeline in response to clock cycles following the first clock cycle. The clock stop pipeline includes a final circuit component to produce a final stop instruction when the intermediate stop instruction and the small phase delay signal of the final integrated circuit internal clock cycle are received at the final circuit component. The final stop instruction is used to lock the integrated circuit internal clock in a single digital state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.